1. Field of the Invention
This invention relates to a method of controlling access to independently controllable memory units commonly shared by data processing units and an access controlling unit including independently controllable memory units commonly shared by data processing units.
2. Description of the Prior Art
An access controlling unit controlling access from a data processing unit to a memory unit in another data processing unit coupled to the data processing unit through a buffer is known. Such a prior method is disclosed in Japanese patent application provisional publication No.5-289987. Another access controlling unit controlling access to a resource commonly shared by data processing units through a common bus and buffers provided to data processing unit is known. Such a prior art access controlling unit is disclosed in Japanese patent application provisional publication No. 3-75959. In this prior art access controlling unit, the data processing unit that has obtained the right to use the common bus can access the shared resource.
In the case of the former access controlling unit, when one data processing unit accesses the shared memory unit, another data processing unit is stopped. Thus, if access to the shared memory unit is frequent, the processing efficiency will decrease.
In the case of the latter access controlling unit, either of the data processing units is stopped only when both data processing units require the common bus at the same time. Thus, the processing efficiency is higher than that of the former data processing unit. However, if it is assumed that there is more than one common resource, though both data processing units access different resources at the same time, the data processing unit without the right to use the common bus is stopped.
In the case of the latter access controlling unit, either of data processing unit is stopped only when both data processing unit require the right of using the common bus at the same time. Thus, the processing efficiency is higher than that of the former data processing unit. However, if it is assumed that there are more than one common resources. Though both data processing units access to different resources at the same time, the data processing unit without right of using the common bus is stopped.
Still another prior art access controlling unit coupled to memory units and data processing unit is known, wherein different data processing units can access different memory units, respectively. FIG. 15 is a block diagram of such a prior art access controlling unit. A control unit 100 for coupling data busses DX and DY from two data processing units X and Y to data buses DA and DB from two memory units A and B is provided as the access controlling unit.
In this example, the data buses DX, DY, DA, and DB have the same bus width (sixteen bits), and the memory units A and B have continuously changing addresses, respectively.
The control unit 100 includes a data path control circuit 110. The data path control circuit 110 includes an X-side loading path unit 111 for coupling either of the data bus DA or DB to the data bus DX in response to the path control signal Sx, a Y-side loading path unit 112 for coupling either of the data bus DA or DB to the data bus DY in response to the path control signal Sy, an A-side storing path unit 113 for coupling either of the data bus OX or DY to the data bus DA in response to the path control signal Sa, and a Y-side storing path unit 114 for coupling either of the data bus DX or DY to the data bus DB in response to the path control signal Sb.
Here, each of the path units 111 to 114 includes a gate circuit having a ti-state buffer, so that turning on the gate circuit enables loading and storing in each of path units 111 to 114. The control unit 100 further includes a control circuit (not shown) for generating the path control signals Sx, Sy, Sa, and Sb in accordance with address signals and various control signals outputted by the data processing units X and Y.
The control circuit discriminates access from each of the data processing units X and Y among to-A-side access, to-B-side access, and no access on the basis of the address, and various control signals from the data processing units X and Y. Next, the control circuit effects the arbitration process for every data processing unit as shown by a flow chart as shown in FIG. 16A.
Here, the data processing units operate synchronously with each other and execute one process at every processing cycle, for example, one clock cycle. Thus, it is assumed that the arbitration process mentioned below is executed at every processing cycle.
When the arbitration process is activated, the control circuit judges whether there is no access in step S510. If there is no access in step S510, processing ends. If there is access, the control circuit judges whether there is collision in step S520. If there is no collision, the control circuit permits the access in step S540.
Comparing the destinations of accesses from the data processing units X and Y provides this judgment. If the destinations are the same, there is collision as shown by the table in FIG. 16B.
If there is collision, the control circuit judges which access has higher priority in step S530. The control circuit permits the access from the data processing unit having a higher priority and inhibits the access from the data processing unit having a low priority in steps S540 and S550.
The aim of the present invention is to provide a superior method of controlling access to memory units and a superior access controlling unit.
According to the present invention, a first aspect of the present invention provides a method of controlling access to a memory device commonly shared by a plurality of data processing units, said memory device including 2M memory units (M being a natural number) which are independently controllable and have the same data bus width as said data processing units, comprising steps of: (a) assigning addresses to each of said memory units such that addresses in each of said memory units change in the same manner as other memory units and corresponding addresses in said memory units vary in accordance with arrangement of said memory units in said memory device; (b) when one of said data processing units requests to read data in said memory device at a data size which is 2k times said data bus width (1xe2x89xa6kxe2x89xa6M and k being a natural number), reading (loading) said data from the corresponding 2k memory units at the same time; and (c) independently supplying each of data from said corresponding 2k memory units 2k times to said one of said data processing units.
According to the present invention, a second aspect of the present invention provides a method based on the first aspect, wherein in step (b), when said one of said data processing unit requests reading (loading) desired data at a desired address at a data size which is 2P times said data bus width (0xe2x89xa6pxe2x89xa6Mxe2x88x921 and p being a natural number), and if any other data processing unit does not request access to said memory device, reading (loading) another data at an address following to said desired address from data processing units other than said one of said data processing units and storing other data in a temporary register as pre-loading data; and after supplying said desired data to said one of said data processing units, when said one of data processing unit requests reading (loading) with an address agreeing with said address, supplying said other data from said temporary register to said one of said data processing units.
According to the present invention, a third aspect of the present invention provides a method based on the second aspect, wherein, when said desired data is other than an instruction for executing a predetermined process in said one of said data processing units, inhibiting reading of said other data.
According to the present invention, a third aspect of the present invention provides a method based on the first aspect, further comprising the steps of: (d) when one of said data processing units requests to store data in said memory device at a data size which is 2k times said data bus width, independently supplying each portion of said data from said one of said data processing unit 2k times and then, storing all portions of said data in the corresponding 2K memory units at the same time.
According to the present invention, a fifth aspect of the present invention provides a method of controlling access to a memory device commonly shared by a plurality of data processing units, said memory device including 2M memory units (M being a natural number) which are independently controllable and have the same data bus width as said data processing units, comprising steps of: (a) assigning addresses to each of said memory units such that addresses in each of said memory units change in the same manner as other memory units and corresponding addresses in said data processing units vary in accordance with arrangement of said memory units in said memory device; (b) when one of said data processing units requests to store data in said memory device at a data size which is 2k times said data bus width (1xe2x89xa6kxe2x89xa6M and k being a natural number); and (c) independently supplying each portion of said data from said one of said data processing units 2k times and then-, storing all portions of said data in the corresponding 2k memory units at the same time.
According to the present invention, a sixth aspect of the present invention provides an access control unit, coupled to a plurality of data processing units and a memory device including 2M memory units which are independently controllable and have the same data bus width as said data processing units (M being natural number), for controlling access from said data processing units to said memory device, addresses in each of said memory units being defined such that said addresses in each of said memory units change in the same manner as other memory units and corresponding addresses in said memory units vary in accordance with arrangement of said memory units in said memory device, said access control unit comprising: reading (loading) temporary registers, each being provided every data processing unit for temporarily storing data read from said memory device; usual reading (loading) means responsive to a reading (loading) request for reading (loading) said data at an address indicated by said reading (loading) request and supplying said data to one of said data processing unit sending said reading (loading) request; simultaneously reading (loading) means for, when said reading (loading) request is for reading (loading) said data at a data size which is 2k times said data bus width (1xe2x89xa6kxe2x89xa6M and k being a natural number), reading (loading) said data at addresses following to said address from the corresponding (2kxe2x88x921) memory units at the same time as said usual reading (loading) means reads said data and storing said data from said addresses following to said address in said reading (loading) temporary registers; and buffer reading (loading) means for successively supplying each of said data from said reading (loading) temporary registers to said one of said data processing units in response to following reading (loading) requests successively made (2kxe2x88x921) times after said reading (loading) request.
According to the present invention, a seventh aspect of the present invention provides an access control unit based on the sixth aspect, further comprising: pre-loading means for, when said one of said data processing unit requests access for reading (loading) desired data at a desired address at a data size which is 2P times said data bus width (0xe2x89xa6pxe2x89xa6Mxe2x88x921 and p being a natural number), and any other data processing unit does not request to access to said memory device, reading (loading) another data at an address following to said desired address from data processing units other than said one of said data processing units and storing another data in said reading (loading) temporary register as pre-loading data; a pre-loading address register for storing a top address of said pre-loading data; and pre-loading data supplying means for supplying said other data from said reading (loading) temporary register to said one of data processing units after supplying said desired data to said one of said data processing units, when said one of data processing units requests following reading (loading) with an address agreeing with said address.
According to the present invention, an eighth aspect of the present invention provides an access control unit based on the seventh aspect, further comprising: pre-loading inhibiting means for discriminating a type of said access requested by said one of said data processing units and inhibiting to read said other data when said access is a type other than an instruction for executing a predetermined process in said one of said data processing units.
According to the present invention, a ninth aspect of the present invention provides an access control unit based on the sixth aspect, further comprising: storing temporary registers, each being provided to every memory unit for temporarily storing said data in each of said memory units; usual storing means responsive to a storing request from one of said data processing units for directly supplying said data outputted from said one of data processing units to one of said memory units indicated by said storing request; buffer storing means for, when said storing request as a first successive storing request is for requesting storing data at a bit size which is 2k times said data bus width (1xe2x89xa6kxe2x89xa6M and k being a natural number), storing first to (2kxe2x88x921)th divided data out of said data in response to said first successive storing request to (2kxe2x88x921)th successive storing requests; simultaneously storing means for, after said divided data has been stored in said storing temporary registers by said buffer storing means, storing said divided data outputted from said one of data processing units in the corresponding 2k memory units together with said first to (2kxe2x88x921)th divided data stored in said storing temporary registers in response to said (2k)th successive storing request.
According to the present invention, a tenth aspect of the present invention provides an access control unit based on the sixth aspect, further comprising arbitration means for, when a collision between accesses from said data processing units to the same memory unit occurs, halting a data processing unit having a lower priority.
According to the present invention, an eleventh aspect of the present invention provides an access control unit based on the tenth aspect, further comprising external priority changing means for changing priorities of said data processing units in response to external operation.
According to the present invention, a twelfth aspect of the present invention provides an access control unit based on the tenth aspect, further comprising automatic priority changing means for changing priorities of said data processing unit in accordance with a predetermined rule at each arbitration by said arbitration means.
According to the present invention, a thirteenth aspect of the present invention provides an access control unit coupled to a plurality of data processing units and a memory device including 2M memory units which are independently controllable and have the same data bus width as said data processing units (M being natural number), for controlling access from said data processing unit to said memory device, addresses in each of said memory units being defined such that said addresses in each of said memory units change in the same manner as other memory units and corresponding addresses in said memory units vary in accordance with arrangement of said memory units in each memory device, said access control unit comprising: storing temporary registers, each being provided every memory unit for temporarily storing said data in each of said memory units; usual storing means responsive to a storing request from one of said data processing units for directly supplying said data outputted from said one of data processing units to one of said memory units indicated by said storing request; buffer storing means for, when said storing request as a first successive storing request is for requesting storing data at a bit size which is 2k times said data bus width (1xe2x89xa6kxe2x89xa6M and k being a natural number), storing first to (2kxe2x88x921)th divided data out of said data in response to said first successive storing request to (2kxe2x88x921)th successive storing requests; simultaneously storing means for, after said divided data has been stored in said storing temporary registers by said buffer storing means, storing said divided data outputted from said one of data processing units in the corresponding 2k memory units together with said first to (2kxe2x88x921)th divided data stored in said storing temporary registers in response to said (2k)th successive storing request